A Scaleable Multiprocessor Architecture with Multiple Read-Write Memory Model

This paper presents a scalable multiprocessor architecture with multiple access memories and multi-way busses. This parallel architecture with more intelligent memory model and efficient multi-way interconnection network organization is called as CRrCW (Concurrent Read and restricted Concurrent Write) scaleable multiprocessor system. The memory and network model provides concurrent memory accesses and more memory bandwidth for a CRrCW scaleable multiprocessor system. Thus, the proposed multiprocessors system with the memory model and network take advantages of both multiprocessor systems with shared memory and distributed memory. In this paper, conventional shared, distributed memory multiprocessor and the CRrCW multiprocessor are examined under various conditions and also compared with each other. A sliding caches memory model is used to reduce the cost of the CRrCW multiprocessor system. A cluster controller is also used to enhance the broadcast and multicast ability of the interconnection network. Simulation results of the sliding caches memory model show that memory requirements of a CRrCW multiprocessor system is almost independent of scale of the multiprocessor. In addition this, simulation results of the interconnection network also show that even small number of the connection per processors greatly enhances the scalability of the multiprocessor system. Two scientific applications, volume visualization and N-body problem, is chosen to examine performance of the system. These applications case studies represent a range of important behaviors found in parallel computing. The CRrCW multiprocessor system with special interconnection network and intelligent memory organization provides high speed-up and efficiency over conventional shared and the distributed memory multiprocessor. Therefore, the CRrCW multiprocessor system is a potential candidate for large-scale parallel computing applications.